電気・電子システムジャーナル

Design and Implementation of Vedic Multipliers Using Reversible Logic Gates

Abstract

Ravi JN, Vijay Prakash AM and Madan S

Implementing the already existing circuits or new circuits using reversible logic has drawn a significant interest in recent years as a promising computing technique having application in low power CMOS, quantum computing, nanotechnology, optical computing …etc. Reversible logic gates offer significant advantages such as high speed, low power, ease of fabrication …etc. Also, circuits designed using these circuits would have better performance as compared to existing circuits. Main goals of reversible logic synthesis are to minimize the garbage, to minimize the delay, to minimize the total number of gates, to minimize the width of the circuit. In this paper, designer implemented 2 × 2 and 4 × 4 bit Vedic multipliers using reversible logic gate.